A low-power minimum distance 1D-search engine using hybrid digital/analog circuit techniques

This Minimum Distance ID-Search Engine (MDSE) realizes the pattern-matching hardware accelerator for the portable multimedia and intelligent processing systems. The chip executes highly parallel computation of L,-norms between an input key and stored multiple reference records, and search of the minimum distance among them in 1 dimensional (1D) memories. According to architectural-level power estimation, the proposed MDSE improves the power reduction by orders of magnitude as compared to the conventional systems, as the number of record increases. Two novel circuits, such as Merged Memory Logic (MML) and Digital/Analog Mixed Winner-Take-All (DAMWTA) circuit, have been implemented with 0.6 pm CMOS technology. The simulation results of the 4bit-8word MDSE show that-the power dissipation (=2.8mW at 3V) of the MML coincides to the estimated power within 43% error, and the worst-case delay of the DAM-WTA is less than 80ns. 1. Architectural-Level Power Estimation The architecture of MDSEs are classified into three different styles shown in Fig. 1 (a)-(c). Assume that 1OMHz (=fs) sampled keys (=Xi) are compared in brute-force manner to the given N records(=Yjj=l,2,... ,N) with 4bit unsigned integer representation. * I 1 -port f IMbit SRAM Ia3 b Found (Records, Y J ---------Address, k (a) The external SRAM and data-paths. (fi , = fs, f, ?= N x fs, f, 3= N x fs, f, 4= N x fs ) (b) The Embedded Memory Logic. (f*.,= fs, fi,Z= N x fs, f2,3= N x fs, fZA4= N x fs) (c) The proposed MDSE. (f3.1= fs, fJe2= fs ) Figure 1. The block diagram of MDSEs. For power estimation in architectural-level, it is necessary to be (realistically) assumed that supply voltage (=Vdd) is fixed within the process constraints and the clock frequency (=fclk) is scaled linearly below the maximum frequency at which the external SRAM can be accessed. Moreover, assumed the fclk can be gated according to the power-down strategies, then the maximum frequency is only needed to compute the minimal number of parallel data-paths. All the power/area libraries have been uniformly adapted for a 0.6 pm CMOS technology, operating at 5V. For the SRAM, we have used the power model of Fujitsu’s lMbit-SRAM[l], whose maximum frequency is 1OOMHz at SV. The other power models have been adopted from the developed models of embedded RAM, registers[2] and data-paths[3], and they have been slightly modified by Constant E-Field (CE) scaling theory[4]. For area estimation, 0.8 pm COMPASS library[5] has been also scaled similarly to the given 0.6 pm CMOS technology. Fig. 2 shows the predicted results of total power and area, neglecting the dashed boxes due to their negligible contribution. Notice that the power which goes into the memory access (c~f~,J dominates the other contributions. In addition, it can be also noticeable that the effective capacitance of an external SRAM is about one order of magnitude larger than that of an embedded RAM. However, we cannot overlook the gap of power dissipation between Fig. 1 (b) and Fig1 .(c) increases as the number of record increases. The reason is that the curve of Figl.(b) increases in proportion to N2, while that of our MDSE increases in portion to N due to the elimination of f2.3. Comparison of Architectures(Fig.1) @ fs=lOMHt, 0.6um tech., vdd=SV, fck=lOOMHz -7-1, -1---, I 1 1 1 t I 5 6 7 8 9 10 LogZ(Nurnber of Records) [x : SRAM+Data-Path] [ o : EML] [ * : MDSE] 1 I 1 LogZ(Number of Records) Figure 2. The estimated results of total power and area. I-214 0-7803-5474-5/99/$10.00 1999 IEEE 2. Merged Memory Logic Circuit Our proposed MML has the following features: Firstly, it is very compact and modular to be expanded further, for the first half adder is a combination of the XOR with positive Manchester carry chains having transmission gate structures. Secondly, for low power consumption, it is designed by signal feedback technique (at MPF)[6] and charge-recycling scheme (at MNE)[7], which will be more useful to speed up the propagation delay as the number of records increases. Finally, it is flexible in adaptation to the change of various functions such as absolute difference calculation, subtraction, and addition, via simple control of (Jo, Co//and Cn. The MML circuit is designed to calculate the absolute difference value between an n-bit input key (=Yn) with n-bit records (=Xn) stored at SRAM in parallel. Fig.3 presents a l-bit MML circuit with a l-bit SRAM cell. Hence, the n-bit MML circuit can be constructed by cascading n l-bit MML circuits like an n-bit ripple carry adder. If CFGl *CSi is high, then the input data ( Yi and % ) can be inserted. As RESET falls to zero, the circuits start to perform two subtractions simultaneously, Xn Yrz and Yfz Xn . Using the most significant bit (=Cn) of these two operations, the multiplexer selects the positive one. Therefore, the output (=Di) gives the absolute difference value (=Fnml). Fig.4 shows the average power dissipation of our 4bit-8word MML over 200ns duration. All the pseudo-random input keys were generated by a 32bit LFSR(Linear Feedback Shift Register). Notice that the power dissipation simulated by HSPICE using the extracted parameters from the chip-layout coincides to the estimated power within 36~59% error. To reduce the area, two subtractors are combined as follows. Pi = Xi 0 E for Xi Yn = xi 0 Yi (1) . for Yn XII Average Power Dissipation of 4bit X 8word MML 20.0m r 18.0m F -simulated at Vdd=W -A--error at Vdd=5V 90 o~-simulated at Vdd=3V --VW error at Vdd=3V iw16.0mt estimated at Vdd=SV 80 Ci = XiYi + Ci-lPi for Xn Yn (2) C/ = XiYi + &Pi for Yn Xn Y ‘0 14.0m m estimated at Vdd=3V 70 .Y Di = Pi Q C,,Ci-l+ C,C:-, ( 1 (where Co = CA = 1) (3) "1 .E .! 1 n -----NW”---.l.D-